
`include "defines.v"
//----------------------------------------------------------------
//Module Name : cpu_top.v
//Description of module:
// cpu + clint
//----------------------------------------------------------------
//Designer:	Tang Pengyu
//Date: 2021/10/07	  
//----------------------------------------------------------------
module ysyx_210195(
  input         clock,
  input         reset,
//  input         io_interrupt,
  input         io_master_awready,
  output        io_master_awvalid,
  output [31:0] io_master_awaddr,
  output [3:0]  io_master_awid,
  output [7:0]  io_master_awlen,
  output [2:0]  io_master_awsize,
  output [1:0]  io_master_awburst,
  input         io_master_wready,
  output        io_master_wvalid,
  output [63:0] io_master_wdata,
  output [7:0]  io_master_wstrb,
  output        io_master_wlast,
  output        io_master_bready,
  input         io_master_bvalid,
  input  [1:0]  io_master_bresp,
  input  [3:0]  io_master_bid,
  input         io_master_arready,
  output        io_master_arvalid,
  output [31:0] io_master_araddr,
  output [3:0]  io_master_arid,
  output [7:0]  io_master_arlen,
  output [2:0]  io_master_arsize,
  output [1:0]  io_master_arburst,
  output        io_master_rready,
  input         io_master_rvalid,
  input  [1:0]  io_master_rresp,
  input  [63:0] io_master_rdata,
  input         io_master_rlast,
  input  [3:0]  io_master_rid
/*
  output        io_slave_awready,
  input         io_slave_awvalid,
  input  [31:0] io_slave_awaddr,
  input  [3:0]  io_slave_awid,
  input  [7:0]  io_slave_awlen,
  input  [2:0]  io_slave_awsize,
  input  [1:0]  io_slave_awburst,
  output        io_slave_wready,
  input         io_slave_wvalid,
  input  [63:0] io_slave_wdata,
  input  [7:0]  io_slave_wstrb,
  input         io_slave_wlast,
  input         io_slave_bready,
  output        io_slave_bvalid,
  output [1:0]  io_slave_bresp,
  output [3:0]  io_slave_bid,
  output        io_slave_arready,
  input         io_slave_arvalid,
  input  [31:0] io_slave_araddr,
  input  [3:0]  io_slave_arid,
  input  [7:0]  io_slave_arlen,
  input  [2:0]  io_slave_arsize,
  input  [1:0]  io_slave_arburst,
  input         io_slave_rready,
  output        io_slave_rvalid,
  output [1:0]  io_slave_rresp,
  output [63:0] io_slave_rdata,
  output        io_slave_rlast,
  output [3:0]  io_slave_rid
*/
);

wire	aw_user_o;		//自定义
wire	[2:0]	aw_prot_o;				//access permissions
wire	aw_lock_o;
wire	[3:0]	aw_cache_o;			//memory types
wire	[3:0]	aw_qos_o;			//Quality of service identifier for a write transaction
wire	[3:0]	aw_region_o;		//多接口时用

wire	w_user_o;
wire	b_user_i = 0;
wire	[2:0]	ar_prot_o;
wire	ar_user_o;
wire	ar_lock_o;
wire	[3:0]	ar_cache_o;
wire	[3:0]	ar_qos_o;
wire	[3:0]	ar_region_o;
wire	r_user_i = 0;

wire	load_clint_en;
wire	clint_w_ena;
wire	[63:0]	load_store_addr;
wire	[63:0]	store_clint_data;
wire	load_clint_en_exe;
wire	[63:0]	load_clint_addr_exe;
	
wire	time_overstep;
wire	[63:0]	load_clint_data_exe;
//wire	[`REG_DATA_LEN-1:0] load_clint_data;
wire 	[31:0]	aw_addr_h;
wire 	[31:0]	ar_addr_h;

ysyx_210195_cpu	ysyx_210195_cpu	
(
	.clock(clock),
    .reset(reset),

//to slave
	//MASTER write addr
	.aw_ready_i(io_master_awready),			//slave -> master,ready to receive write address
	.aw_valid_o(io_master_awvalid),			//master -> slave,write address valid
	.aw_addr_o({aw_addr_h,io_master_awaddr}),		//write sddress
	.aw_id_o(io_master_awid),			//write address channel ID
	.aw_user_o(aw_user_o),		//自定义
	.aw_prot_o(aw_prot_o),				//access permissions
	.aw_len_o(io_master_awlen),			//burst lenth = aw_len + 1
	.aw_size_o(io_master_awsize),			//本次burst中，一次transferde的字节数
	.aw_burst_o(io_master_awburst),			//burst_type
	.aw_lock_o(aw_lock_o),
	.aw_cache_o(aw_cache_o),			//memory types
	.aw_qos_o(aw_qos_o),			//Quality of service identifier for a write transaction
	.aw_region_o(aw_region_o),		//多接口时用
	
	//master write data
	.w_ready_i(io_master_wready),
	.w_valid_o(io_master_wvalid),
	.w_data_o(io_master_wdata),
	.w_strb_o(io_master_wstrb),				//标志有效位
	.w_last_o(io_master_wlast),						//标志最后一次传输
	.w_user_o(w_user_o),
	
	//write response
	.b_ready_o(io_master_bready),
	.b_valid_i(io_master_bvalid),
	.b_resp_i(io_master_bresp),
	.b_id_i(io_master_bid),
	.b_user_i(b_user_i),
	
	//read address channel
	.ar_ready_i(io_master_arready),
	.ar_valid_o(io_master_arvalid),
	.ar_addr_o({ar_addr_h,io_master_araddr}),
	.ar_prot_o(ar_prot_o),
	.ar_id_o(io_master_arid),			//read address channel identifier
	.ar_user_o(ar_user_o),
	.ar_len_o(io_master_arlen),
	.ar_size_o(io_master_arsize),
	.ar_burst_o(io_master_arburst),
	.ar_lock_o(ar_lock_o),
	.ar_cache_o(ar_cache_o),
	.ar_qos_o(ar_qos_o),
	.ar_region_o(ar_region_o),
	
	//read data channel
	.r_ready_o(io_master_rready),
	.r_valid_i(io_master_rvalid),
	.r_resp_i(io_master_rresp),
	.r_data_i(io_master_rdata),
	.r_last_i(io_master_rlast),
	.r_id_i(io_master_rid),
	.r_user_i(r_user_i),
	
	
	//clint
	.load_clint_en(load_clint_en),
	.clint_w_ena(clint_w_ena),
	.load_store_addr(load_store_addr),
	.store_clint_data(store_clint_data),
	.load_clint_en_exe(load_clint_en_exe),
	.load_clint_addr_exe(load_clint_addr_exe),
	
	.time_overstep(time_overstep),
	.load_clint_data_exe(load_clint_data_exe)
//	.load_clint_data(load_clint_data)

);

ysyx_210195_clint_reg	ysyx_210195_clint_reg(
	.clk(clock),
	.rst(reset),
//	.load_clint_en(load_clint_en),
	.clint_w_ena(clint_w_ena),
	.load_store_addr(load_store_addr),
	.store_clint_data(store_clint_data),
	.load_clint_en_exe(load_clint_en_exe),
	.load_clint_addr_exe(load_clint_addr_exe),
	
//	.load_clint_data(load_clint_data),
	.load_clint_data_exe(load_clint_data_exe),
	.time_overstep(time_overstep)
	
	
);

endmodule